A low-dropout (or LDO) linear voltage regulator is a DC linear voltage regulator, which can operate with a very small input-output differential voltage. The LDO linear voltage regulator is commonly referred to as simply “LDO.” The advantages of a low dropout voltage regulator include a lower minimum operating voltage, better supply rejection, and lower output noise when compared to switching type regulators. The main components of a typical LDO linear voltage regulator may include a power FET (e.g., power MOSFET or an equivalent component) and a differential amplifier (i.e., an error amplifier). The FET and the differential amplifier cooperate to regulate the output voltage. The differential amplifier has two inputs: one is used to monitor the output voltage, which is typically determined by a ratio of two resistors, and the other is a stable voltage reference (e.g. a bandgap reference). If the output voltage rises too high (or drops too low) relative to the reference voltage, the signal that controls the power FET changes to maintain a constant output voltage.
An example of an LDO is illustrated in FIG. 1, which shows a schematic block diagram of an LDO linear voltage regulator (100). As shown in FIG. 1, the feedback network (106), including a resistor divider (103) and an error amplifier (102), regulates the DC output voltage Vout to a desired level given by Vout=Vref*(1+R2/R1). The error amplifier (102) may be a single stage or a multi-stage amplifier. The resistor R2 may be a short circuit, and/or the resistor R1 may be an open circuit in some architectures. The pass element Mpass (101) may be either a field effect transistor (FET), a bipolar transistor, an LDMOS transistor or a FinFET device, and may be of either n-type or p-type. Multi-stage and high-gain amplifiers are typically used as the implementation of the error amplifier (102) in the feedback network (106). CL (104) represents the sum of a physical external capacitor, any other capacitor that models the input capacitance of the load, and any additional parasitic capacitance. The external capacitor is not located inside the same silicon die as the LDO and instead is placed on the printed circuit board (PCB) or inside the microchip package. Some LDO architectures do not require an external capacitor, CL (104) (commonly referred as capacitor-less LDO), while other LDO architectures require this external capacitor, CL (104). The current source, IL (105) models the current that is being consumed by the load connected at the output terminal, Vout, of the linear voltage regulator.
Architectures that require an external capacitor to guarantee the stability of the LDO usually have superior performance over capacitor-less architectures. These performance parameters include both superior power supply rejection (PSR) and load transient regulation. Power supply rejection is the ability of the LDO to reject any noise coming from the supply through the Vin terminal in FIG. 1. Throughout this disclosure, the terms, “power supply,” “supply,” “Vin,” and “Vin terminal” may be used interchangeably to refer to the power source input to a voltage regulator. Load transient regulation is the change in the output voltage Vout when there is an instantaneous change in the load current, IL (105). Load transient regulation lower than 20 mV is typically achieved when there is a step in the load current from/to 10 mA to/from 300 mA in 1 μsec, and an external capacitor is used. However, when the load current changes from/to values lower than 1 mA to/from a higher value, the output voltage can drop significantly reaching a load transient regulation higher than 0.5 V (in some cases it can reach a value higher than 1V) even with an external capacitor.
FIG. 2 (200) shows the simulation results of the output voltage of a conventional prior art LDO (100) when the pass element is implemented using an N-type FET. In this simulation, the load current changes from 0 mA to 100 mA in 1 μsec and an external capacitor (104) of 1 μF is used as the load capacitor. As depicted, the output voltage drops by 0.6 V during the load transient phase. Such a performance is not acceptable for many linear voltage regulators. The main reason for the degradation of load transient regulation is explained as follows:
Assume that the linear voltage regulator is initially supplying the maximum load current. In the example shown in FIG. 2 (200), this value of current is 100 mA. When the load current suddenly drops to a value lower than 1 mA, the linear voltage regulator keeps supplying the 100 mA until the loop responds to the change in the load current. This 100 mA charges the output capacitor, Cext, instantaneously, forcing the output voltage to increase by a value ΔVout. As a result, the input to the differential amplifier (102) increases, forcing the gate of the pass element Mpass (101) to suddenly drop to zero, and thus, Mpass is turned off. During this phase, the voltage regulator loop which consists of elements (101), (102), (103), (104), (105), and (106), does not respond to any load or supply changes, and the loop does not regulate the output voltage based on input voltage changes. The linear voltage regulator (100) exits this state when the excess voltage (ΔVout), is discharged through the feedback network R1 and R2, and the load current IL. The discharge time can be much larger than 1 msec. When the output voltage reaches the correct regulator output level, the input to the differential amplifier (102) decreases, and thus the gate of the pass element Mpass increases. This forces Mpass to start working again and the loop can now settle and regulate the output voltage to the desired voltage value.
In the case that the load current increases before the output voltage settles to the desired value, the output drops significantly reaching a ΔVout change of at least 0.6 V as demonstrated by FIG. 2. This is because during this event, the loop of the linear voltage regulator is broken as explained above, and the pass element (101) Mpass is off and it is not capable of supplying the required load current. The simulation result in FIG. 2 shows that the prior art linear regulators cannot be used in many applications that have a sudden change in the load current from/to values lower than 1 mA to/from higher values.
The load switch regulator has substantially the same structure as the LDO voltage regulator. The main difference between the LDO and the load switch regulator is the reference voltage (Vref). In the case of the LDO voltage regulator, Vref is supply independent and usually generated by a bandgap reference voltage circuit. In the case of the load switch regulator, Vref is a scaled (and filtered) version of the DC value of the supply (Vin). Thus, the DC level of the output voltage Vout changes proportionally with the DC level of the input voltage Vin. Accordingly, the block diagram shown in FIG. 1 may also be used to represent a load switch regulator with an external capacitor or without an external capacitor (a capacitor-less load switch regulator). Similar to the conventional LDO voltage regulators, the prior art load switch regulators have a limited load transient regulation performance of about 1V for a step in the load current from/to less than 1 mA to/from 100 mA or larger load currents in 1 μsec. Throughout this disclosure, the terms “load switch regulator,” “load switch linear voltage regulator,” and “load switch” may be used interchangeably. Further, the term “LDO/load switch linear voltage regulator” refers to either an LDO or a load switch depending on specific configurations of the reference voltage used.
U.S. Pat. No. 8,344,713 B2 discusses an analog circuit where a load transient circuit is introduced to enhance the transient load regulation response for large variations in load current. This is achieved by sensing the variations in the output voltage through capacitive coupling, and then controlling the gate of the pass element Mpass. Thus, this approach senses the output voltage and controls directly the gate of the pass element. The circuit is implemented using two capacitors and two current mirrors. This approach does not solve the issue that is being addressed in this patent because if the loop stops regulating the output, the circuit is not able to instantaneously recover the state of the output voltage. In addition, this approach typically results in a degraded power supply rejection performance.
U.S. Pat. No. 7,714,553 B2 discusses an analog circuit where a load transient regulation circuit is proposed to enhance the transient load regulation response for large variations of the load current. This is achieved by comparing a feedback signal to a defined voltage called Vref. Then, the gate of the pass element is discharged to overcome the large overshoot/undershoot of the output voltage. It is important to emphasize that this approach senses a feedback signal and compares it to a constant reference voltage. The control signal is then applied to the gate of the pass element. A similar approach in which the sense signals are the same as the ones presented in U.S. Pat. No. 7,714,553 B2 was discussed in U.S. Pat. No. 6,201,375, but the control signal is applied to the output of the linear regulator.